The semiconductor industry continues to strive for improvements in the speed and performance of semiconductor devices. Strained silicon technology enhances carrier mobility in both n-channel and p-channel devices, and thus improves device speed and performance.
One technique for producing strained silicon involves growing silicon on relaxed silicon germanium (Si/SiGe) structures. There is a large mismatch in the cell structure between the Si and SiGe layers. This mismatch causes a pseudomorphic layer of Si on relaxed SiGe to be under a tensile strain that modifies the band structure and enhances carrier transport in the Si layer. In an electron inversion layer, the subband splitting is larger in strained Si because of the strain-induced band splitting in addition to that provided by quantum confinement. For example, the ground level splitting (E0(d4)−E0(d2)) in a MOS inversion layer at 1 MV/cm transverse field is ˜120 meV for unstrained Si and 250 meV for strained Si. The increase in energy splitting reduces inter-valley scattering and enhances NMOSFET mobility, as demonstrated at low (<0.6 MV/cm) and higher (˜1 MV/cm) vertical fields. The scaled transconductance (gm) is also improved due to the reduced density of states and enhanced non-equilibrium transport.
One method for forming the Si/SiGe layer involves epitaxially growing the Si and SiGe layers using an ultra-high vacuum chemical vapor deposition (UHVCVD) process. The UHVCVD process is a costly and complex process. The Ge content is graded in steps to form a fully relaxed SiGe buffer layer before a thin (˜20 nm) strained Si channel layer is grown. X-ray diffraction analysis can be used to quantify the Ge content and strain relaxation in the SiGe layer. The strain state of the Si channel layer can be confirmed by Raman spectroscopy. One proposed back end approach for straining silicon applies uniaxial strain to wafers/dies after the integrated circuit process is complete. The dies are thinned to membrane dimensions and then affixed to curved substrates to apply an in-plane, tensile strain after device manufacture.
There is a need in the art to provide improved strained semiconductor films and devices that incorporate the strained films, and to provide improved methods for forming strained semiconductor films.